1. Field of the Invention
The present invention relates to a flash memory device and a method for fabricating the same, and more particularly, to a flash memory device and a method for fabricating the same, which is suitable for improving integration in a SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) cell.
2. Discussion of the Related Art
A typical example of a nonvolatile memory device, in which data can be rewritable, is EEPROM (Electrically Erasable Programmable Read Only Memory). Generally, EEPROM devices use a floating gate type cell.
With rapid development of high-integration devices, the size of the floating gate type cell has generally decreased according to the related art. However, beyond a certain size, it is difficult to decrease the cell size since a relatively high voltage is generally used in programming and erasing modes, and it is difficult to obtain sufficient process margin for defining tunneling. For these (and other) reasons, various nonvolatile memory devices such as SONOS, FeRAM, SET and NROM have been studied actively as a substitute for the floating gate type cell. Among them, SONOS cell has attracted great attention as a nonvolatile memory device that can substitute for the floating gate type cell.
Hereinafter, a related art SONOS type nonvolatile memory device will be described with reference to the accompanying drawings.
FIG. 1 is a layout of showing a unit cell of an SONOS type nonvolatile memory device according to the related art. FIG. 2A is a cross sectional view along I–I′ of FIG. 1. FIG. 2B is a cross sectional view along II–II′ of FIG. 1. FIG. 2C is a cross sectional view of showing a pattern defect due to misalignment.
As shown in FIG. 1, FIG. 2A and FIG. 2B, the unit cell of the SONOS type nonvolatile memory device according to the related art includes a semiconductor substrate 11, a device isolation layer 12, an ONO layer 13, and a gate electrode 14. At this time, the device isolation layer 12 (an STI, or Shallow Trench Isolation, structure) is formed in the semiconductor substrate 11, to divide the semiconductor substrate 11 into a field region and an active region. Also, the ONO layer 13 is formed by sequentially stacking a lower oxide layer 13a, a nitride layer 13b and an upper oxide layer 13c in order, wherein the lower oxide layer 13a is used as a tunnel oxide layer, the nitride layer 13b functions as a memory (storage) layer, and the upper oxide layer 13c functions as a gate dielectric or blocking layer for preventing the loss of electric charges. Then, the gate electrode 14 is formed on the ONO layer 13. In addition, source and drain regions 15a and 15b are formed at both sides of the gate electrode 14 in the active region of the semiconductor substrate 11. Then, a drain contact hole 16 is formed in the drain region 15b, for connection with an upper line.
In this case, the device isolation layer 12 is formed of an insulating layer in an STI (Shallow Trench Isolation) process. Recently, as dimensions in design rules for high integration semiconductor device decrease, the distance between the device isolation layers 12 becomes small. Accordingly, when the drain region 15b is formed in the semiconductor substrate 11 between the device isolation layers 12, a width of the drain region 15b is also decreased, so that it is difficult to obtain a sufficient interval between the drain contact hole 16 and the device isolation layer 12.
In case of misalignment when forming the drain contact hole 16, as shown in FIG. 2C, the drain contact hole 16 may be formed above the device isolation layer 12 as well as above the drain region 15b. That is, when forming the drain contact hole 16, a portion of the semiconductor substrate 11 adjacent to the device isolation layer 12 may be etched, thereby generating junction leakage. Accordingly, the memory device may operate incorrectly or fail.